This paper describes several new algorithms for computing lower bounds on the length of the schedule and the number of functional units in high-level synthesis.

Dynamically Reconfigurable Field Programmable Gate Arrays (DR FPGAs) change many of the basic assumptions of what hardware is. DR FPGA-based dynamically reconfigurable computing has become a powerful methodology for achieving high performance while minimizing the resource required in the implementation of many applications. The key to harnessing the power of DR FPGAs for most applications is to...

A New System-Level Speci cation Transformation Frank Vahid Department of Computer Science University of California, Riverside, CA 92521 [email protected] Abstract We introduce a new system-level speci cation transformation called procedure exlining. Exlining is the problem of replacing sequences of statements by procedure calls, which is the opposite problem of inlining. Procedures are used by s...

In this paper, we present a power management technique targeted towards high-level synthesis of data-dominated behavioral descriptions. Our method is founded on the observation that variable assignment can significantly affect power management opportunities in the synthesized architecture. Based on this observation, we present a procedure for constraining variable assignment, so that the functi...

One of the primary advantages of a high-level synthesis system is its ability to explore the design space. This paper presents several methodologies for design space exploration that compute all optimal tradeo points for the combined problem of scheduling, clock length determination, and module selection. We discuss how each methodology takes advantage of both the structure within the design sp...

A high-level test generation algorithm SWIFT is proposed which incorporates a symbolic scheduling procedure, derived from high-level synthesis applications, to resolve decision conflicts during test generation. SWIFT uses the induced fault model to generate functional tests that guarantee detection of low-level structural faults. When applied to functional models of representative 74Xseries, IS...

Signiicant power reduction can be obtained in the datapath of a CMOS VLSI circuit if data characteristics are carefully exploited. An improved approach that achieves such reduction by using a new model relating important data characteristics to the transition activity in static CMOS circuits is presented. Speciically, relationships between xed-point, two's complement data and 0 ! 1 transition a...

This paper describes an improved transformational approach to the scheduling problem in high-level synthesis. Based on an existing approach called SALSA [NES90], it uses more powerful transformations and lower bounds on scheduling cost to quickly find highquality schedules of data-oriented Control-Data Flow Graphs. Results show the ability to find very good schedules for difficult scheduling pr...

The last two decades have seen tremendous effort on the development of high-level synthesis algorithms for efficient realization of the multiplication of a variable by a set of constants using only addition, subtraction, and shift operations. These algorithms generally target the minimization of the number of adders and subtractors, assuming that shifts are realized using only wires due to the ...

| Since manufacturing processes inherently uctuate, LSI chips which are produced from the same design have di erent propagation delays. However, the di erence in delays caused by the the process uctuation has rarely been considered in most high-level synthesis systems which were developed before. This paper presents a new approach to module selection in high-level synthesis, which exploits di e...