For many years, research on FPGA-type programmable hardware architectures has focused mainly on optimising regular non-hierarchical architectures. In the exploration of their design space, some design parameters have a significant impact on the layout area, which is directly related to interconnect delay. An estimation of this impact can be derived from a prediction of the area of the basic FPG...

Cloud computing is an established paradigm for end users to access resources. infrastructure providers seek maximize accepted requests, meet Service Level Agreements (SLAs), and reduce operational costs by dynamically allocating Virtual Machines (VMs) physical nodes. Many solutions have been presented manage cloud infrastructure, however, these tend be centralized suffer in their ability mainta...

This paper presents a modified 32-bit ROM-based Direct Digital Frequency Synthesizer (DDFS). Maximum output frequency of the DDFS is limited by the structure of the accumulator used in the DDFS architecture. The hierarchical pipeline accumulator (HPA) presented in this paper has less propagation delay time rather than the conventional structures. Therefore, it results in both higher maximum ope...