A 6-bit 20 GS/s 16-channel time-interleaved (TI) analog-to-digital converter (ADC) using a two-step flash ADC with sample-and-hold (S/H) sharing technique and gain-boosted voltage-to-time (VTC) is presented for high-speed wireline communication systems. By one S/H between coarse fine stages in the ADC, input bandwidth as well area power efficiency can be improved without gain error ADCs. Thanks...

A 3-bit ADC for X-band applications that can work at a sampling rate of 11 GS/s is presented in this paper. Current comparators are used to achieve the high sampling rate of 11 GHz at X-band. A 3-bit current-steering DAC is also designed for testing the high-speed ADC. The ADC-DAC RFIC is implemented in a 0.12 μm SiGe technology and occupies a core area of 1.0 x 0.8 mm. The ADC can operate with...

The ADC architecture and timing diagram are shown in Figure 1. The converter consists of a 7b coarse flash stage, a 7b digital-to-analog converter (DAC), a subtractor. and a 6b fine flash stage. One-of-n decoders and ROhIs are used to convert the thermometer code outputs ofthe two flash stages to binarydata, that is thencorrecteddigitally to produce the final output. One bit ofredundancy. or ov...

Today, given the extensive use of convertors in industry, reducing the power consumed by these convertors is of great importance. This study presents a new method to reduce consumption power in Flash ADC in 65nm CMOS technology. The simulation results indicate a considerable decrease in power consumption, using the proposed method. The simulations used a frequency of 1 GHZ, resulting in decreas...

This paper presents a new method to reduce consumption power in flash ADC in 65nm CMOS technology. This method indicates a considerable reduction in consumption power, by removing comparators memories. The simulations used a frequency of 1 GHZ, resulting in decreased consumption power by approximately 90% for different processing corners. In addition, in this paper the proposed method was desig...

■ Memories – 2 Kbytes single voltage extended Flash (XFlash) Program memory with Read-Out Protection In-Circuit Programming and In-Application programming (ICP and IAP) Endurance: 1K write/erase cycles guaranteed Data retention: 20 years at 55 °C – 128 bytes RAM ■ Clock, Reset and Supply Management – Low voltage supervisor (LVD) for safe power-on/off – Clock sources: Internal trimmable 8 MHz RC...

A novice advanced architecture of 8-bit analog to digital converter is introduced and analyzed in this work. The structure proposed ADC based on the sub-ranging which a 4-bit resolution flash-ADC utilized. designed by employing comparator equipped with common mode current feedback gain boosting technique (CMFD-GB) residue amplifier. 8 bits can achieve speed 140 megasamples per second. at 10 MHz...