This paper addresses the efficient implementation of a robust gradient-based optical flow model in a low-power platform based on a multi-core digital signal processor (DSP). The aim of this work was to carry out a feasibility study on the use of these devices in autonomous systems such as robot navigation, biomedical assistance, or tracking, with not only power restrictions but also real-time r...

It is a trend for the large hydropower bases to transport electricity consuming center with High Voltage Direct Current (HVDC) transmission lines. The fault of HVDC has great significance impact on units in islanding sending AC grid. In this paper, hybrid simulation system established analyze dynamic characteristic system. based Real Time Digital Simulator (RTDS) and Signal Processor (DSP). ele...

The purpose of this paper is to present the experimental results a Modular Multilevel Converter – MMC using algorithms Nearest Level Modulation (NLM) and capacitor voltage balancing greatly reduce switching frequency as well harmonic components at AC side. in consists 12 submodules (SMs) generate 13–level waveform. In case, system converter requires large number I/O signal ports. However, conve...

Self-Timed FPGA Systems p. 21 XC6200 Fastmap Processor Interface p. 36 The Teramac Configurable Computer Engine p. 44 Telecommunication-Oriented FPGA and Dedicated CAD System p. 54 A Configurable Logic Processor for Machine Vision p. 68 Extending DSP-Boards with FPGA-Based Structures of Interconnection p. 78 High-Speed Region Detection and Labeling Using an FPGA Based Custom Computing Platform ...

A smart home controller that responds to natural language input is demonstrated on an Intel® embedded processor. This device contains two DSP cores and a neural network co-processor which share 4MB SRAM. An embedded configuration of the Intel® RealSpeechTM speech recognizer and intent extraction engine runs on the DSP cores with neural network operations offloaded to the co-processor. The proto...

Programmable devices are a key technology for the design of embedded systems, such as in the consumer electronics market. Processor cores are used as building blocks for more and more embedded system designs, since they provide a unique combination of features: exibility and reusability. Processor-based design implies that compilers capable of generating e cient machine code are necessary. Howe...

This paper presents an FPGA implementation of a 3-layer perceptron using the FDFM (Few DSP blocks and Few block RAMs) approach implemented in the Xilinx Virtex-6 family FPGA. In the FDFM approach, multiple processor cores with few DSP slices and few block RAMs are used. We have implemented 150 processor cores for perceptrons in a Xilinx Virtex-6 family FPGA XC6VLX240T-FF1156. The implementation...

This paper presents an instruction level power model for a very long instructions word (VLIW) single instruction multiple data (SIMD) digital signal processor (DSP). We show that power consuming memory accesses can be reduced in such SIMD processor architectures with an appropriate network connecting the parallel register files and/or data paths. Several network topologies are analyzed for a va...

Despite the progress made in developing more advanced compilers for embedded systems, programming of embedded high-performance computing systems based on Digital Signal Processors (DSPs) is still a highly skilled manual task. This is true for single-processor systems, and even more for embedded systems based on multiple DSPs. Compilers often fail to optimise existing DSP codes written in C due ...

A standard design methodology for embedded processors today is the system-on-a-chip design with potentially multiple heterogeneous processing elements on a chip, such as a very long instruction word (VLIW) processor, digital signal processor (DSP), and field-programmable gate array. To be able to program these devices, we need compilers that are capable of generating efficient code for the diff...