This paper presents a compact model for organic thin-film transistors fabricated in the staggered or coplanar device architecture which includes short-channel effects related to potential barrier channel region, manifest themselves as threshold voltage roll-off, drain-induced lowering, and subthreshold swing degradation. Furthermore, effect of non-linear injection due work-function mismatch bet...

Articles you may be interested in Evaluation of pulsed laser annealing for flexible multilayer MoS2 transistors Appl. Schottky-barrier lowering in silicon nanowire field-effect transistors prepared by metal-assisted chemical etching Appl. Measurement of low Schottky barrier heights applied to metallic source/drain metal–oxide–semiconductor field effect transistors

We report the experimental demonstration of deepsubmicrometer inversion-mode In0.75Ga0.25As MOSFETs with ALD high-k Al2O3 as gate dielectric. In this letter, n-channel MOSFETs with 100–200-nm-long gates have been fabricated. At a supply voltage of 0.8 V, the fabricated devices with 200–130-nm-long gates exhibit drain currents of 232–440 μA/μm and transconductances of 538–705 μS/μm. The 100-nm d...

In this paper, gate leakage current has been mitigated by the use of novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure for the first time. A compact analytical model has been developed to study the gate leakage behaviour of proposed MOSFET structure. The result obtained has found good agreement with the Sentaurus Simulation. Fringing gate electric field...

The effect of gate length and Thickness on the characteristic curve of drain-source current verse gate voltage in ZnO and GaAs MOSFETs have been simulated. Three transistors with gate lengths of 30, 40 and 50 nm are simulated. Simulations show that with a fixed channel length, when the gate length is increases, the output drain current would be increased, the Moreover, with increasing oxide Thi...

In this article, a new structure is presented for MOS (Metal Oxide Semiconductor)-like junctionless carbon nanotube field effect transistor (MOS-like J-CNTFET), in which dual material gate with different work-functions are used. In the aforementioned structure, the size of the gates near the source and the drain are 14 and 6 nm, respectively, and the work-functions are equal and 0.5 eV less tha...

In this paper, novel hybrid MOSFET(HMOS) structure has been proposed to reduce the gate leakage current drastically. This novel hybrid MOSFET (HMOS) uses source/drain-to-gate non-overlap region in combination with high-K layer/interfacial oxide as gate stack. The extended S/D in the non-overlap region is induced by fringing gate electric field through the high-k dielectric spacer. The gate leak...

In this article, a new structure is presented for MOS (Metal Oxide Semiconductor)-like junctionless carbon nanotube field effect transistor (MOS-like J-CNTFET), in which dual material gate with different work-functions are used. In the aforementioned structure, the size of the gates near the source and the drain are 14 and 6 nm, respectively, and the work-functions are equal and 0.5 eV less tha...

We demonstrated a nanowire gate-all-around (GAA) negative capacitance (NC) tunnel field-effect transistor (TFET) based on the GaAs/InN heterostructure using TCAD simulation. In gate stacking, we proposed tri-layer HfO2/TiO2/HfO2 as high-K dielectric and hafnium zirconium oxide (HZO) ferroelectric (FE) layer. The GAA-TFET overcomes thermionic limitation (60 mV/de...