Abstract: In this paper we present ultra low-voltage and high speed CMOS domino Carry gates. For supply voltages below 325mV the delay for the proposed ultra low-voltage Carry gates are approximately 5% relative to a complementary CMOS Carry gate. Furthermore, the Energy Delay Product is less than 1% relative to complementary CMOS Carry gate at the same supply voltage. Different domino Carry ga...

We describe an implementation of Letchford’s domino-parity inequalities for the (symmetric) traveling salesman problem. The implementation includes pruning methods to restrict the search for dominoes, a parallelization of the main domino-building step, heuristics to obtain planar-support graphs, a set of safe-shrinking routines, a random-walk heuristic to extract additional violated constraints...

The recent work of Bonnafé et al. [2] shows through two conjectures that r-domino tableaux have an important role in Kazhdan-Lusztig theory of type B with unequal parameters. In this paper we provide plactic relations on signed permutations which determine whether given two signed permutations have the same insertion r-domino tableaux in Grafinkle’s algorithm [3]. Moreover, we show that a parti...

Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favored in high performance designs because of the speed advantage offered over static CMOS logic circuits. The main drawbacks of dynamic logic are a lack of design automation, a decreased tolerance to noise and increased power Consumption. Dynamic CMOS circuits, featuring a high spee...

The aim of this note is to give a quick derivation of Theorem 1 using the techniques developed in [1] and the skew domino Cauchy identity. Let Gλ/μ(X; q) = ∑ D q spin(D)xweight(D) be the spin-weight generating function of domino tableaux with shape λ/μ; see for example [1]. Here we will use the convention that spin(D) is equal to half the number of vertical dominoes in D. Though not stated expl...

Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose several domino logic circuit techniques to improve the robustness and performance along with leakage power. Lower total power consumption is achieved by utilizing proposed techniques. According to the simulations in TSMC 65 nm CMOS process, the proposed c...

A novel technique using a keeper with a simultaneous low supply voltage and low body voltage is proposed to improve the overall performance of high fan-in OR gates without modifying the physical dimensions of the keeper. Simulation results of a 16-input domino OR gate using 45 nm CMOS technology show that the proposed technique could trade off between a high power/speed efficient operation and ...

In this paper, footless domino logic buffer circuit is proposed. It minimizes redundant switching at the dynamic and the output nodes. This circuit passes propagation of precharge pulse to the dynamic node and avoids precharge pulse to the output node which saves power consumption. Simulation is done using 0. 18μm CMOS technology. We have calculated the power consumption, delay and power delay ...

The proliferation of both Partially Depleted SiliconOn-Insulator (PD-SOI) technology and domino circuit styles has allowed for increases in circuit performance beyond that of scaling traditional bulk CMOS static circuits. However, interactions between dynamic circuit styles and PD-SO1 complicate testing. This paper describes the issues of testing domino circuits fabricated in SO1 technology and...

Domino effects have been shown to hinder a tight prediction of worst case execution times (WCET) on real-time hardware. First investigated by Lundqvist and Stenström, domino effects caused by pipeline stalls were shown to exist in the PowerPC by Schneider. This paper extends the list of causes of domino effects by showing that the pseudo LRU (PLRU) cache replacement policy can cause unbounded e...