In the present paper we show a dichotomy theorem for the complexity of polynomial evaluation. We associate to each graph H a polynomial that encodes all graphs of a fixed size homomorphic to H . We show that this family is computable by arithmetic circuits in constant depth if H has a loop or no edge and that it is hard otherwise (i.e., complete for VNP, the arithmetic class related to #P ). We...

The recent discovery of the memristor has renewed the interest for fast arithmetic operations via high-radix numeric systems. In this direction, a conceptual solution for high-radix memristive arithmetic logic units (ALUs) was recently published. The latter combines CMOS circuitry for data processing and a reconfigurable “segmented” crossbar memory block. In this paper we build upon such a conc...

We study limitations of polynomials computed by depth two circuits built over read-once polynomials (ROPs) and depth three syntactically multi-linear formulas. We prove an exponential lower bound for the size of the ΣΠ ] arithmetic circuits built over syntactically multi-linear ΣΠΣ ] arithmetic circuits computing a product of variable disjoint linear forms on N variables. We extend the result t...

The modified SNIP indicator of Elsevier, as recently explained by Waltman et al. SNIP value was obtained by dividing an arithmetic average in the numerator by a median value in the denominator which results in a quotient without the possibility of specifying the statistical uncertainty in the indicator. Instead of dividing aggregates, one should normalize observed against expected values in ter...

Arithmetic circuits have been used as tractable representations of probability distributions, either generated from models such as Bayesian networks, sum-product networks and Probability Sentential Decision Diagrams, or directly from data. An interesting question is how we can incorporate uncertain evidence, which specifies that the marginal probabilities of a variable has to undergo certain ch...

This paper presents FloPoCo, a framework for easily designing custom arithmetic datapaths for FPGAs. Its main features are: an important basis of highly optimized arithmetic operators, a unique methodology for frequency-directed pipelining the designed circuits and a flexible test-bench generation suite for numerically validating the designs. The framework was tested for designing several compl...

SNAP The Stanford Sub-nanosecond arithmetic processor is an interdisciplinary e ort to develop validated theory, and tools for realizing an arithmetic processor with execution rates under 1ns. The project has targeted the full spectrum of tradeo s from algorithms, circuit optimizations, system issues, and development of metrics to characterize processors.

The author uses an elementary lemma on primes dividing binomial coefficients and estimates for primes in arithmetic progressions to sharpen a theorem of J. Rickert on simultaneous approximation to pairs of algebraic numbers. In particular, it is proven that max {∣∣∣∣√2− p1 q ∣∣∣∣ , ∣∣∣∣√3− p2 q ∣∣∣∣} > 10−10q−1.8161 for p1, p2 and q integral. Applications of these estimates are briefly discussed.

In this paper we investigate the implementation of basic arithmetic functions, such as addition and multiplication, in Single Electron Tunneling (SET) technology. First, we describe the SET equivalent of two conventional design styles, namely the equivalents of Boolean CMOS and threshold logic gates. Second, we propose a set of building blocks, which can be utilized for a novel design style, na...

In this paper different distributed Arithmetic (DA) architectures are proposed for Finite Impulse Response (FIR) filter. FIR filter is the main part of the Digital Signal Processing. In Digital Signal Processing we can use Multiply Accumulator Circuit (MAC) and DA for filter design.MAC consumes more power and area because of multiplier and adder circuit. The design distributed arithmetic is run...