This paper reports the development of a low-power switchedcurrent algorithmic A/D converter based on a new algorithm, providing the bit conversion in three-cycles. The converter uses modified SI type current copiers to reduce the overall area and power consumption. The analog portion of the converter occupies only 0.35mm area in 3μm CMOS technology. The simulation results show that the converte...

This letter presents an inductor-loaded 2:1 regenerative frequency divider operating up to 331.2 GHz in an InP HBT process, which, to the best of authors’ knowledge, is the fastest frequency divider reported thus far. On-wafer measurement shows that the divider is operating from 304.8 GHz to 331.2 GHz, with output power from 27 dBm to 12.3 dBm (no probe loss correction), while dissipating 85.5 ...