This paper presents an improved measure for the dynamic functionality of a logic circuit, called delay fault probability (DFP). The new measure reflects both the nominal delay of the paths and the fact that only few paths are critical for path delay fault testing. An efficient distributed algorithm for computing DFP is presented. The experimental results show that, in contrast to DFP, the conve...

The probabilistic methods for power estimation in combinational circuits are classified in two categories according to the adopted gate-delay model. The zero and real gate-delay power estimation methods. Under zero delay model, assuming spatiotemporal independence among the circuit signals, the switching activity, E(sw), of a circuit node, x, is given by ) 1 ( 2 2 ) ( 1 1 0 1 x x x x p p p p sw...

This article presents a commutated-inductor–capacitor (commutated- $LC$ ) or switched- circuit that acts as radio frequency (RF) delay line. Thanks to its linear-periodically time-varying (LPTV) operation and fully passive implementat...

In this paper, the various low power delay product full adder circuits have been analyzed. The adder is the fundamental blocks of any arithmetic circuit, so even a small reduction power or delay leads to improved performance of the circuit with optimal power saving. A 10T adder technique is the famous low power delay product full adder circuits with minimum transistor count. A new 10T technique...

|A high drive CMOS bu er circuit characterized by a voltage transfer characteristic (VTC) with low threshold voltages and hysteresis is proposed. The proposed circuit is capable of restoring slow transition times and distorted input signals with a minimum delay penalty. Due to the hysteresis characteristic of this bu er, a comparison with a Schmitt-trigger is provided. An important application ...

The resistive-capacitive behavior of long interconnects which are driven by CMOS gates is analyzed in this paper. The analysis is based on the π-model of an RC load and is developed for submicron devices. Accurate and analytical expressions for the output voltage waveform, the propagation delay and the short circuit power dissipation are derived by solving the system of differential equations w...

In this paper, footless domino logic buffer circuit is proposed. It minimizes redundant switching at the dynamic and the output nodes. This circuit passes propagation of precharge pulse to the dynamic node and avoids precharge pulse to the output node which saves power consumption. Simulation is done using 0. 18μm CMOS technology. We have calculated the power consumption, delay and power delay ...