Signalling over long interconnect is a dominant issue in electronic chip design in current technologies, with the device sizes getting smaller and smaller and the circuits becoming ever larger. Repeater insertion is a well established technique to minimise the propagation delay over long resistive interconnect. In deep sub-micron technologies, as the wires are spaced closer and closer together ...

This paper is based on analysis of a common source - common gate low noise transconductance amplifier (CS-CG LNTA). Conventional noise analyses equations are modified by considering to the low output impedance of the sub-micron transistors and also, parasitic gate-source capacitance. The calculated equations are more accurate than calculated equations in other works. Also, analyses show that th...

SUMMARY In order to shorten the time-to-market, Application-Specic Integrated Circuits (ASIC's) are designed from a library of pre-dened layout implementations for register-transfer modules such as multipliers, adders, RAM, ROM, etc. Current approaches to selecting the implementations from the library usually deal with their timing-area estimates and do not consider delay of the intermodule wir...

This paper reports a design of a bonding pad oriented square-shape ESD (electrostatic discharge) protection structure. The novel ESD protection structure provides adequate protection for IC chips against ESD pulses in all directions. The structure features deep snapback symmetric characteristics, low discharging impedance, low holding voltage, and flexible triggering voltage. It passed 14KV HBM...

High leakage current in deep sub-micron regimes is a significant contributor to the power dissipation of CMOS circuits as the CMOS technology scales down. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low power applications. . This paper explores transistor leakage mechanisms and devi...

.........................................................................................................................3 Introduction....................................................................................................................4 Fault Model Notation and Error Control Scheme for S2S Buses on NoC [1]...............5 Analysis of Error Recovery Schemes for Networks on Chips ...

IDDQ test is a valuable test method for semiconductor manufacturers. However, its effectiveness is reduced for deep sub-micron technology chips due to rising background leakage. Current two test methods that promise to extend the life of IDDQ test are Current Ratio and Delta-IDDQ. Although several studies have been reported on these methods, their effectiveness in detecting defects has not been...

This paper investigates the effect of optimizing the transistor finger width on the performance of high-speed analogue circuits in deep sub-micron processes, demonstrated in a 28nm High-K/Metal Gate (HKMG) CMOS technology process. Silicon proven results demonstrate that the oscillator with a finger width of 440nm gives the best performance based on the Figure of Merit (=142) among the benchmark...