نتایج جستجو برای: custom instruction
تعداد نتایج: 62212 فیلتر نتایج به سال:
the purpose of the present study was to see which one of the two instruction-processing instruction (pi) and meaningful output based instruction (mobi) accompanied with prompt and recast- is more effective on efl learners’ writing accuracy. in order to homogenize the participants in term of language proficiency a preliminary english test (pet) was administrated between 74 intermediate students ...
http://dx.doi.org/10.1016/j.micpro.2014.05.007 0141-9331/ 2014 Elsevier B.V. All rights reserved. ⇑ Corresponding author. Tel.: +98 2182084920; fax: +98 2188778690. E-mail addresses: [email protected] (A. Yazdanbakhsh),mehdikamal@ ut.ac.ir (M. Kamal), [email protected] (S.M. Fakhraie), [email protected] (A. Afzali-Kusha), [email protected] (S. Safari), [email protected] (M. Pedram). 1 Present a...
Extracting appropriate custom instructions is an important phase for implementing an application on an extensible processor with a reconfigurable functional unit (RFU). Custom instructions (CIs) are usually extracted from critical portions of applications. It may not be possible to meet all of the RFU constraints when CIs are generated. This paper addresses the generation of mappable CIs on an ...
This article presents an instruction-set extension to the open-source RISC-V ISA (RV32IM) dedicated ultra-low power (ULP) software-defined wireless IoT transceivers. The custom instructions are tailored needs of 8/16/32-bit integer complex arithmetic typically required by quadrature modulations. proposed occupies only two major opcodes and most designed come at a near-zero energy cost. Both ins...
The M•CORE microRISC architecture has been developed to address the growing need for long battery life among today’s portable applications. In this paper, we will present the low-power design techniques and architectural trade-offs made during the development of this processor. Specifically, we will discuss the initial benchmarking, the development of the Instruction Set Architecture (ISA), the...
This paper presents an application of a neural-network algorithm, the Kohonen feature map, to security monitoring in power transmission systems, and its implementation on parallel hardware. The computational requirements of the application led to the development of an SIMD processor array dedicated to neural networks. The heart of this system is a systolic array of simple processing elements (P...
A 400-MIPS/200-MFLOPS (peak) custom 64-b VLSI CPU chip is described. The chip is fabricated in a 0.75pm CMOS technology utilizing three levels of metalization and optimized for 3.3-V operation. The die size is 16.8 mm X 13.9 mm and contains 1.68M transistors. The chip includes separate 8-kilobyte instruction and data caches and a fully pipelined floating-point unit (FPU) that can handle both IE...
Umbra is an efficient and scalable memory shadowing tool built on top of DynamoRIO, which is a state-ofthe-art runtime code manipulation system. Using the APIs provided by DynamoRIO, Umbra inserts code into the applications runtime instruction stream to perform memory address translation from application memory to shadow memory. Umbra also provides a simple interface that enables developers to ...
Three generations of Alpha microprocessors have been designed using a proven custom design methodology. The performance of these microprocessors was optimized by focusing on high-frequency design. The Alpha instruction set architecture facilitates high clock speed, and the chip organization for each generation was carefully chosen to meet critical paths. Digital has developed six generations of...
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