In this paper, an isolation enhanced multiway power divider for wideband beamforming array is proposed. This method is based on the concept which converts the divider into multi-section stepped impedance transformer. In addition to this scheme, lumped inductors and capacitors are incorporated in isolation networks to enhance the isolation bandwidth of the divider. In/Output reflection and isola...

This paper reviews the relevance of the widely used device metrics fT, fmax as well as the recently introduced device metrics fA and fcross for broadband circuit design. Usually, IC processes are benchmarked on the basis of their fT and fmax. For most circuit applications however, there is only an indirect relation between fT, fmax and circuit bandwidths. Since the differential pair amplifier i...

This paper first presents the architecture of a frequency synthesizer which can support multistandard wireless systems of GPS, Galileo, and WCDMA standards. Then, a programmable integer/fractional combined frequency divider (CFD), which is the key building block of the proposed frequency synthesizer, is designed and implemented by using 0.18μm RF CMOS process. The CFD mainly consists of an inte...

-A lumped element 180 Wilkinson divider consisting of 11 elements was presented in 2003. It used a conventional Wilkinson divider, a -90 and a +90 phase shifter of πand T-type. In this paper, that of 10 elements is newly presented. Frequency characteristics of the two 180 Wilkinson dividers and those of a rat-race divider known as an out of phase circuit are discussed. Key-Words: Wilkinson divi...

This work describes the design of a double-precision radix-8 divider. Low-power techniques are applied in the design of the unit, and energy-delay tradeoffs considered. The energy dissipation in the divider can be reduced by up to 70% with respect to a standard implementation not optimized for energy, without penalizing the latency. The radix-8 divider is compared with one obtained by overlappi...

The increasing computation requirements of modern computer applications have stimulated a large interest in developing extremely high-performance floating-point dividers. A variety of division algorithms are available, with SRT being utilized in many computer systems. A careful analysis of SRT divider topologies has demonstrated that a relatively simple divider designed in an aggressive circuit...

Introduction: Fractional-N frequency dividers allow PLL Synthesizers to have frequency resolutions finer than the reference frequency. However, there are two disadvantages in a fractional-N divider, namely, fractional spurs generation and frequency range limitation. A fractional-N divider generates fractional spurs due to the fixed pattern of the dual-modulus divider [1]. The frequency range of...