The increasing complexity of systems-on-a-chip with the accompanied increase in their test data size has made the need for test data reduction imperative. In this paper, we introduce a novel and efficient testindependent compression technique based on geometric shapes. The technique exploits reordering of test vectors to minimize the number of shapes needed to encode the test data. The test set...

Larger designs and the growing population of non-stuck defects have led many companies to adopt test compression techniques. In fact, the Embedded Deterministic Test (EDT) technology within TessentTM TestKompress® has now been used in over one billion production chips. There has been a surge of compression techniques promoted in the industry since Tessent TestKompress was released in 2001. So, ...

&AS DESIGN SIZES have grown larger and semiconductor manufacturing processes have scaled down to extremely small feature sizes, the number of test vectors needed to thoroughly test a chip has exploded. To alleviate this potentially road-blocking issue to further technology scaling, test data compression became an active research topic in the late 1990s, and has now become a standard offering wi...

Test data volume is now recognized as a major contributor to the cost of SoC manufacturing testing, as it leads to an increasing testing time. In this paper we present the progress of the dictionary based test data volume reduction (compression) methods.

Ohletz [1] described a mixed signal circuit architecture which can be reconfigured to allow built-inself-test of both analogue and digital parts. In testing the analogue section an on board test signal can be generated from digital components, the analogue test output fed through an A-D converter and the resulting digital bit stream used as the input to a digital signature analyser. Clearly suc...

1 This paper presents a test input data compression technique, which can be used to reduce input test data volume, test time, and the number of required tester channels. The technique is based on grouping data packets and applying various binary encoding techniques, such as Huffman codes and Golomb-Rice codes. Experiments on actual industrial designs and benchmark circuits show an input vector ...

In this paper, we present a low power architecture for scan-path. This architecture is suitable when it is used with a test compression. Based on data compression methodology, the vector set is partitioned so that the segments repeated in every scan can be removed. Here, it is not needed to change all bits of scan path during the new scan path where new test vector will be filled. In this way, ...

This paper presents a new pattern run-length compression method whose decompressor is simple and easy to implement. It encodes 2|n| runs of compatible or inversely compatible patterns, either inside a single test data segment or across multiple test data segments. Experimental results show that it can achieve an average compression ratio of 67.64% and considerable test application time savings.

A novel test vector compressioddecompression technique is proposed for reducing the amount of test data that must be stored on a tester and transferred to each core when testing a core-based design. A small amount of on-chip circuitry is used to reduce both the test storage and test time required for testing a core-based design. The fully specified test vectors provided by the core vendor are s...