A technique has been developed for efficiently mapping arbitrary MOS circuit schematics into corresponding layouts. Since transistor sizings are preserved during this transformation to layout, this synthesis methodology can effectively be applied to optimized circuit schematics which typically include such sized transistors. The technique is based on a restructuring of the circuit description h...

Several 64-bit adders have been designed and their ezpected yield has been estimated. OUT Tesults show that the yield of VLSI adders can be improved by modifying the layout of the ol.iginal design and/or by choosing a dzfferent layout and circuit structure. In certain situations, these approaches can improve the yield by 10% to 17%.

In this paper, we describe how we have exploited the advantages of various methods for device recognition and modeling in a layout-to-circuit extractor, called Space. Hence, we have obtained a program that, for different technologies, can quickly translate a large layout into an equivalent network. The network includes layout parasitics of the interconnects and can directly be simulated by vari...

In many high-performance VLSI designs, including all recent Intel microprocessors, datapath is implemented in a bit-sliced structure to simultaneously manipulate multiple bits of data. The circuit and layout of such structures are largely kept the same for each bitslice to achieve maximal performance, higher designer productivity, and better layout density. There are very few tools available t...

Power reduction in CMOS platforms is essential for any application technology. This is a direct result of both lateral scaling—smaller features at higher density, and vertical scaling—shallower junctions and thinner layers. For achieving this power reduction, solutions based on process-device and process-integration improvements, on careful layout modification as well as on circuit design are i...

This paper presents an automatic layout design system for analog integrated circuits. It is tailed for analog circuit designers so that they can bring their special knowledge and experience into the synthesis process to create high quality layouts. Designers can write and maintain their own technology and application independent module generators for subcircuits in a module generator environmen...

The primary focus of this work is on the generation of layout-aware symbolic performance models (SPMs), for parasitic-inclusive large analog circuits, by using exact hierarchical symbolic analysis. Two problems arise while generating these SPMs. The first problem is the symbolic analysis of large networks. We propose a new hierarchical symbolic analysis technique, that takes the modular approac...

Manual placement is commonly used in FPGA circuit design in order to achieve better resultsthan would be generated by automatic place and route algorithms. However, explicit place-ment of individual components in parameterised descriptions is tedious and error-prone. Inthis thesis we present a framework for the design and verification of parameterised hardwarelibraries with layo...

A design model to find the optimized device dimensions and layout spacings on the input ESD clamp devices is developed in this work to keep the total input capacitance almost constant, even if the analog signal has a varying input voltage. An analog ESD protection circuit has been designed to solve ESD protection challenge on the analog pins for highfrequency applications. The device dimension ...

Most real world problems especially circuit layout and VLSI design are too complex for any single processing technique to solve in isolation. Stochastic, adaptive and local search approaches have strengths and weaknesses and should be viewed not as competing models but as complimentary ones. This paper describes the application of a combined Tabu Search 1] and Genetic Algorithm heuristic to gui...