A new four-phase clock generator for the four-phase charge pumping circuits for very low supply voltages using 0.5pm double poly CMOS technology to generate high boosted voltages is presented. With the new clock generator, the ten-stage charge pump can efficiently pump to 9V at supply voltage of 1V.

An optimal loop parameter design method of charge pump PLLs for jitter transfer characteristic optimization is proposed. Based on the linear model of charge pump PLLs, the relationship between PLLs’ loop parameters and jitter transfer characteristic is illustrated. Using the proposed optimal design method, a design example is done and the expected simulation result is obtained.

A delay-locked loop (DLL) based built-in self test (BIST) circuit has been designed with a 0.18 μ m TSMC process (CM018) to test chip I/O speeds, specifically, the setup and hold times of I/O registers or buffers. The frequency lock range of the DLL is 150-600 MHz (4x). The DLL uses a combined phase detector and charge pump circuit (PD+CP) for increased speed and reduced jitter. The DLL also em...

Ion pump controllers are often considered just accessories needed to power ion pumps. Only basic parameters such as the maximum power and the communication interface are considered relevant, with the power usually being overspecified, resulting in needlessly expensive controllers. However, a properly designed controller can substantially improve the ion pump performance. A controller with varia...

To ensure qualification of charge-pump locked-loop (CPPLL), a complete built-in self-test (BIST) scheme should provide functions of measurement of the clock jitter and detection of faults in CP-PLL. This paper proposes a low cost BIST structure providing both the faults detected and timing jitter measured. The structure based on the proposed time-to-digital converter (TDC), which has high resol...

The CP T symmetry of relativistic quantum field theory requires the total lifetimes of particles and antiparticles be equal. Detection of p lifetime shorter than τp ∼ > O(10 32) yr would signal breakdown of CP T invariance, in combination with B–violation. The best current limit on τ p , inferred from cosmic ray measurements, is about one Myr, placing lower limits on CP T –violating scales that...

This paper investigates the design and performance of the PLL (Phase Locked Loop). The proposed PLL designed with PFD (Phase Frequency Detector), CP (Charge Pump), first order Low Pass Filter and CS-VCO (Current Starved-Voltage Control Oscillator), in this paper the designed PFD used for proposed PLL is free from dead zone. The VCO used for the designed PLL shows larger tuning range and high ga...

Molecular dynamics is of fundamental interest in natural science research. The capability of investigating molecular dynamics is one of the various motivations for ultrafast optics. We present our investigation of photoionization and nuclear dynamics in methyl iodine (CH3I) molecule with an X-ray pump X-ray probe scheme. The pump–probe experiment was realized with a two-mirror X-ray split and d...

In the paper, a programmable phase-locked loop (PLL) based ISM band fractional-N frequency synthesizer, commonly used in wireless communication system, is presented. The third order error-feedback Delta-Sigma modulator and high linearity offset phase frequency detector (PFD)/ Charge Pump (CP) are adopted to reduce close-in phase noise due to ∆Σ quantization noise folding. Automatic calibration ...

A fully integrated dual-mode frequency synthesizer for GSM and Wideband CDMA (WCDMA) is presented. The synthesizer is designed to maximize hardware sharing between the two modes by applying fractional frequency synthesis to GSM mode and integer frequency synthesis to WCDMA mode. The shared components include phase frequency detector (PFD), charge pump (CP), loop filter, integer frequency divide...