A classic experiment used in testing for ESP abilities has the following general form. A deck of cards, consisting of a, identical cards of type i, 1 I i I r, is shuffled and placed face down (in most such experiments r = 5 and a, = 5 for 1 I i _( 5). The subject then attempts to correctly guess the type of each card as the cards are sequentially removed from the deck. In previous work [2,3], s...

Innovative synthesis for testability strategies aim at considering testability while synthesizing a circuit, whereas conventional design for testability methods modify the design after the circuit structure is synthesized. We describe a synthesis approach that maps a behavioral FSM description into a testable gate-level structure. The term “testable” in this context, besides implying the existe...

Jin-Ho Ahn et al. 475 Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the p...

Testing should be evaluated as the ability of the test patterns to cover realistic faults, and high quality IC products demand high quality testing. We use a test strategy based on physical design for testability (to discover both open and short faults, which are difficult or even impossible to detect). Consequentially, layout level design for testability (LLDFI') rules have been developed, whi...