A deterministic-partitioning technique and an improved analysis scheme for fault diagnosis in Scan-Based BIST is proposed. The incorporation of the superposition principle to the analysis phase of the diagnosis algorithm improves diagnosis times significantly; furthermore, the deterministic partitioning approach results in even further reductions in diagnosis times together with higher predicta...

Self-repairing system is alternative for fault tolerant systems. They lose efficiency when the circuit size increases, due to the extra hardware. In existing system, they used four spare cells for one working cell for cell replacement.In proposed system, there is no need to use spare cells permanently.In proposed system, we have taken RISC processor as a working cell for our consideration. BIST...

We propose several improvements to a previously proposed scheme of built-in test pattern generation for synchronous sequential circuits. The basic scheme consists of a parametrized structure for test pattern generation, where parameter values are determined randomly. The proposed improvements consist of an improved structure for test pattern generation that allows more flexibility in the determ...

In this letter a histogram-based BIST (Built-In Self-Test) approach for deriving the main characteristic parameters of an ADC (Analog to Digital Converter) such as offset, gain and non-linearities is proposed. The BIST uses a ramp signal as an input signal and two counters as a response analyzer to calculate the derived static parameters. Experimental results show that the proposed method reduc...

The paper presents a new approach to transparent BIST for wordoriented RAMs which is based on the transformation of March transparent test algorithms to the symmetric versions. This approach allows to skip the signature prediction phase inherent to conventional transparent memory testing and therefore to significantly reduce test time. The hardware overhead and fault coverage of the new BIST sc...

This paper presents a segment weighted random built-in self test (SWR-BIST) technique for low power testing. This technique divides the scan chain into segments of different weights. Heavily weighted segments have more biased probability than lightly weighted segments. Heavily weighted segments are placed closer to the end of scan chain than the lightly weighted segments so the scan-in transiti...

This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduce board/system manufacturing test cost as well as to improve diagnosability of memory and memory-interconnect failures. The proposed methodology incorporates a significant amount of programmability (including programmable...

In this paper we present a new test set embedding method for test-per-clock BIST schemes. The method works efficiently with fully specified as well as partially specified test sets and requires a number of clock cycles equal to the size of the test set. The resulting test pattern generation mechanism (TPG) compares favourably in terms of area implementation and test application time to already ...

This paper presents a method for deriving a BIST specification from the initial specification of datapaths. This method minimizes BIST area overhead under test time constraint while guaranteeing a user chosen fault coverage. The designer can thus explore a wide range of solutions and keep the one that best fits with design constraints. Results show great improvements over lower level techniques.

Input vector monitoring concurrent BIST schemes are the class of online BIST techniques that overcomes the problems appearing separately in online and in offline BIST in a very effective way. This paper briefly presents an input vector monitoring concurrent BIST scheme, which monitors a set of vectors called window of vectors reaching the circuit inputs during normal operation, and the use of a...