Built-In Self-Test for logic circuits or logic BIST is gaining popularity as an effective solution for the test cost, test quality, and test reuse problems. Logic BIST implements most of ATE functions on chip so that the test cost can be reduced through less test time, less tester memory requirement, or even a cheaper tester. Logic BIST applies a large number of test patterns so that more defec...

BACKGROUND Previous studies found a complex relationship between area-level socioeconomic status (SES) and walkability. These studies did not include neighborhood dynamics. Our aim was to study the association between area-level SES and walkability in the city of Madrid (Spain) evaluating the potential effect modification of neighborhood dynamics. METHODS All census sections of the city of Ma...

Delay testing that requires the application of consecutive two-pattern tests is not an easy task in a scan-based environment. This paper proposes a novel approach to the delay fault testing problem in scan-based sequential circuits. This solution is based on the combination of a BIST structure with a scan-based design to apply delay test pairs to the circuit under test.

Power dissipation during test application is an emerging problem due to yield and reliability concerns. This paper focuses on BIST for RTL data paths and discusses testability trade-offs in terms of test application time, BIST area overhead and power dissipation.