AbstractIn this work faster unsigned multiplication has been achieved by using a combination of High Performance Multiplication [HPM] column reduction technique and implementing a N-bit multiplier using 4 N/2-bit multipliers (recursive multiplication) and acceleration of the final addition using a hybrid adder. Low power has been achieved by using clock gating technique. Based on the proposed t...

In this paper, we propose two 2’s-complement fixed-width Booth multipliers that can generate an n-bit product from an n-bit multiplicand and an n-bit multiplier. Compared with previous designs, our multipliers have smaller truncation error, less area, and smaller time delay in the critical paths. A four-step approach is adopted to search for the best errorcompensation bias in designing a multip...

In many of cryptographic schemes, the most time consuming basic arithmetic operation is the finite field multiplication and its hardware implementation may require millions of logic gates. It is a complex and costly task to develop such large finite field multipliers which will always yield error free outputs. In this effect, this paper considers fault tolerant multiplication in finite fields. ...

Booth encoded Multiplier is used to reduce the hardware utilization in chip level designing in VLSI projects. The present project is focusing on designing and developing a powerful Booth encoded multiplier integrated with Carry Select Adder [CSLA]. Primarily the on hand Booth encoding multiplier is used in multiplication operations based on signed numbers only. The multipliers such as braun arr...

This paper studies the effect of high performance pipelined GF(2 256 ) bit-serial multiplier on elliptic curve point operations. A 3-stage pipelined version of the Massy-Omura GF(2 m ) normal basis multiplier for 160 ≤ m ≤ 256 was studied in terms of area overhead and throughput improvement. Simple gate area and delay models were used to estimate the throughput of the pipelined and the non-pipe...

Modulo multiplication plays an important role in the Fermat number transform and residue number systems; the diminished-1 representation of numbers has been found most suitable for representing the elements of the rings. Existing algorithms for modulo multiplication either use recursive modulo addition, or a regular binary multiplication integrated with the modulo reduction operation. Although ...

This work proposes a processor architecture for elliptic curves cryptosystems over fields GF (2 m). This is a scalable architecture in terms of area and speed that exploits the abilities of reconfigurable hardware to deliver optimized circuitry for different elliptic curves and finite fields. The main features of this architecture are the use of an optimized bit-parallel squarer, a digit-serial...

Elliptic Curve Cryptography appeared in 1985 and since became an increasingly important crypto-system in public-key cryptography. Numerous articles have come to improve the field. One of these milestones is Edwards Curves which appeared in 2007 and proposed advantageous properties against SPA attacks. This thesis proposes the design, implementation and comparison of several small co-processors ...

An efficient Lookup Table (LUT) design for memory-based multiplier is proposed.  This multiplier can be preferred in DSP computation where one of the inputs, which is filter coefficient to the multiplier, is fixed. In this design, all possible product terms of input multiplicand with the fixed coefficient are stored directly in memory. In contrast to an earlier proposition Odd Multiple Storage ...

We present a hardware architecture for parallel innerproduct array computation in very high dimensional feature spaces, towards a general-purpose kernel-based classiJer and function approximator: The architecture is internally analog with fully digital interface. On-chip analog jinegrain parallel processing yields real-time throughput levels for high-dimensional (over 1,000per chip) classificat...