Over the last 2-3 years, there has been a major change in the IC industry from being predominantly “functionalbased testing” to being predominantly “scan-based testing” (for new design starts). As recently as 2-3 years ago, the topic of panels was “Is scan-based testing feasible for all products?” The question has now changed to “Can we completely avoid functional testing?” I believe the same t...

A Low Transition LFSR(LT-LFSR) designed by modifying Linear Feedback Shift Register is proposed to produce low power test vectors which are given to Circuit under Test (CUT) to reduce the power consumption by CUT. This technique of generating low power test patterns is performed by increasing the co-relativity between the consecutive vectors by reducing the number of bit flips between successiv...

This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate efficient patterns to be used during BIST test pattern generation. The main idea is that test patterns detecting random pattern resistant faults are not embedded in a pseudo–random sequence as in existing techniques, but rat...

High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution. By proving the effectiveness ...

Design of an adaptive built-in-self-test (BIST) scheme for detecting multiple stuck-open faults in a CMOS complex cell is proposed. The test pattern generator (TPG) adaptively generates a subset of singleinput-change (SIC) test pairs based on the past responses of the circuit under test (CUT). The design is universal, i.e., independent of the structure and functionality of the CUT. The average ...

In this paper, a new algorithm and a new BIST structure for efficiently testing dual port memories that is used widely as embedded memory, is proposed. The proposed test algorithm is able to detect the dual port memories faults and has shorter test time and the test patterns in comparison to existing test algorithms. In addition, the presented BIST has efficient structure that requires lesser h...

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This paper presents aa new test resource partitioningg scheme that is aa hybridd approachh betweenn external testingg andd BIST. It reduces tester storage requirements anddtesterbandwidthhrequirementsbyordersof magnitude comparedd too conventional external testing, but requires muchh less areaa overheadd thann aa full BIST implementationn providingg the same fault coverage. The proposedd approa...

A new hybrid BIST scheme is proposed which is based on using an “incrementally guided LFSR.” It very efficiently combines external deterministic data from the tester with on-chip pseudo-random BIST. The hardware overhead is very small as a conventional STUMPS architecture [1] is used with only a small modification to the feedback of the LFSR which allows the tester to incrementally guide the LF...

BIST is a technique aimed to: Avoiding the usage of expensive ATE Increase the fault tolerance since it add more access to the internal points Allow the application of at-speed test and reduce the test time. It is mandatory to consider the BIST as a test solution when the design flow and the design area can afford it.