Nanoelectronic devices and interconnects will most likely exhibit substantial performance variability. Delivering high performance under such uncertainty conditions will require implementing more complex control and communication mechanisms between system components, in comparison to those used state of the art synchronous design. A key issue becomes thus to assess how the increased densities a...

This paper proposes new scheduling methods for asynchronous circuits with bundled-data implementations. Since operations in asynchronous circuits start after the completion of a previous operation, this method approximates the set of start times for each operation using the delay of the resources. Next, this method decides on control steps from the approximated sets of start times, which are us...

Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This paper introduces a new approach to verify circuits whose behavior is independent of component delays (delay-insensitive). It shows that for a particular way of implementing a delay-insensitive circuit, through a Null Convention Logic methodology, the complexity of the ...

The object of this article is the analysis of asynchronous circuits for speed independence or delay insensitivity. The circuits are specified as a netlist of logic functions describing the components. The analysis is based on a derivation of an event specification of the circuit behavior in a form of a signal graph. Signal graphs can be viewed either as a formalization of timing diagrams, or as...

Design tools for embedded reactive systems commonly use a model of computation that employs both synchronous and asynchronous communication styles. We form a junction between these two with an implementation of synchronous languages and circuits (Esterel) on asynchronous networks (POLIS). We implement fact propagation, the key concept of synchronous constructive semantics, on an asynchronous no...

This paper is aimed at generation of automated test pattern for asynchronous circuits based on genetic algorithm. Asynchronous circuits without global clocks are hard to test due to the lack of testing techniques. The testing of asynchronous design involves basic element like C-element, completion detector in handshake controller and logic design. The main contribution is to generate optimized ...

As demand rises for circuits with higher performance, higher complexity, and decreased feature size, asynchronous (clockless) paradigms will become more widely used in the semiconductor industry, as evidenced by the International Technology Roadmap for Semiconductors’ (ITRS) prediction of a likely shift from synchronous to asynchronous design styles in order to increase circuit robustness, decr...

Though asynchronous design has been studied for decades, some objective design diicul-ties made synchronous design style more suitable for commercial applications. The promise of no clock skew, the higher degree of modularity, the low power consumption, have generated a resurgence of interest of the scientiic community for asynchronous logic. More than two decades of uncontrasted dominion of sy...

The preex problem is to compute all the products x 1 x 2 x k , for 1 k n, where is an associative binary operation. We start with an asynchronous circuit to solve this problem with O(log n) latency and O(n log n) circuit size, with O(n)-operations in the circuit. Our contributions are: (i) A modiication to the circuit that improves its average-case latency from O(log n) to O(log log n) time; an...

This paper presents an ultra-low power circuit design methodology which combines the MultiThreshold CMOS (MTCMOS) technique with quasi delay-insensitive (QDI) asynchronous logic, in order to solve the three major problems of synchronous MTCMOS circuits: (1) Sleep signal generation, (2) storage element data loss during sleep mode, and (3) sleep transistor sizing. In contrast to most power reduct...