For a locally compact group G we look at the group algebras C 0 (G) and C * r (G), and we let f ∈ C 0 (G) act on L 2 (G) by the multiplication operator M (f). We show among other things that the following properties are equivalent: 1. G has a compact open subgroup. 2. One of the C *-algebras has a dense multiplier Hopf *-subalg-ebra (which turns out to be unique). 3. There are non-zero elements...

Abstract Let G be a locally compact unimodular group, and let $\phi $ some function of n variables on . To such , one can associate multilinear Fourier multiplier, which acts -fold product the noncommutative $L_p$ -spaces group von Neumann algebra. One may also define an associated Schur Schatten classes $S_p(L_2(G))$ We generalize well-known transference results from linear case to case. In pa...

A finite group G is said to be efficient if G has a presentation 〈 X | R 〉 where |R| = |X|+rank(M(G)) where M(G) is the Schur multiplier of G; see for example [14]. The efficiency of direct powers, G, of a finite group G has been studied over a number of years, see for example [5], [8] and [14]. In [6] the problem of proving that G is efficient for all n ∈ N, in the case of an imperfect group, ...

Let G be a finite p-group of order pn with |G′| = pk, and let M(G) denote its Schur multiplier. A classical result of Green states that |M(G)| ≤ p 1 2 n(n−1) . In 2009, Niroomand, improving Green’s and other bounds on |M(G)| for a non-abelian p-group G, proved that |M(G)| ≤ p 2 (n−k−1)(n+k−2)+1. In this paper, we prove that a bound, obtained earlier by Ellis and Wiegold, is stronger than that o...

The paper presents the concepts behind the "Urdhva Tiryagbhyam Sutra" and "Nikhilam Sutra" multiplication techniques. It then shows the architecture for a 16×16 Vedic multiplier module using Urdhva Tiryagbhyam Sutra. The paper then extends multiplication to 16×16 Vedic multiplier using "Nikhilam Sutra" technique. The 16×16 Vedic multiplier module using Urdhva Tiryagbhyam Sutra uses four 8×8 Ved...

In this paper different low power 8x8 bit multipliers which are implemented with Tanner Tool v13.0 at 250MHz and 500MHz frequency with 65nm technology which is having a supply voltage 1.0v. There are different CMOS multiplier circuits are analyzed which are Array multiplier, Wallace tree multiplier, Row bypass Braun multiplier, Column bypass Braun multiplier, Row and Column bypass Braun multipl...

This paper presents the design and implementation of signed-unsigned Modified Booth Encoding (SUMBE) multiplier. The present Modified Booth Encoding (MBE) multiplier and the Baugh-Wooley multiplier perform multiplication operation on signed numbers only. The array multiplier and Braun array multipliers perform multiplication operation on unsigned numbers only. Thus, the requisite of the modern ...

The paper presents FPGA implementation of a spectral sharpening process suitable for speech enhancement and noise reduction algorithms for digital hearing aids. Booth and Booth Wallace multiplier is used for implementing digital signal processing algorithms in hearing aids. VHDL simulation results confirm that Booth Wallace multiplier is hardware efficient and performs faster than Booth’s multi...

Abstract—In this paper, a novel Chinese abacus multiplier is presented. The architecture of a 4-bit multiplier is demonstrated. The simulation results of our work are compared with the 4-bit Braun array multiplier. The 0.35μm and 0.18μm TSMC CMOS technologies are used in the simulation. The delay time of the abacus multiplier is at least 63% less than that of Braun array multiplier for 0.18μm t...

We designed a VLSI chip of FFT multiplier based on simple Cooly Tukey FFT using a floating-point representation with optimal data length based on an experimental error analysis. The VLSI implementation using HITACHI CMOS 0.18μm technology can perform multiplication of 2 to 2 digit hexadecimal numbers 19.7 to 34.3 times (25.7 times in average) faster than software FFT multiplier at an area cost ...