The aim of this paper is to present an approach that allows the generation of VHDL from system level specifications in SDL. Our approach overcome the main known problem encountered by previous work which is the communication between different processes. We allow SDL communication to be translated into VHDL for synthesis. This is made possible by the use of an intermediate form that support a po...

17 to their colleagues of CHARME for many helpful discussions and friendly cooperation over many years. 16 Many research groups have proposed formal semantics for VHDL, to apply formal verification techniques on designs described in that language. The FSM model for clock synchronized circuits closest to ours is Bull's [15], but currently only machines with identical state encodings can be compa...

A simple formal semantics for the standard hardware description language vhdl is set out in functional style. The presentation comprises an executable speci-cation for a synchronously clocked vhdl simulator.

The paper outlines the increasing popularity of Hardware Description Languages (HDL), the advantages of VHDL and the reasons it gained an important position in engineering education. Special attention is paid to some difficulties that students meet when VHDL is first introduced to them. The good practices and recommendations are considered and an approach to help the students to overcome these ...

This paper presents a study on the VHDL implementation of a class of binary irregular structured LDPC codes (IS-LDPC) applied to 100 Gbps optical networks. A comparison between two iterative decoding algorithms for irregular structured LDPC codes, sum-product based on loglikelihood ratio and min-sum, is used to define the best choice for implementation. The performances of IS-LDPC codes are eva...

In a VHDL-based design flow for application specific integrated circuits, VITAL provides a uniform methodology for developing ASIC libraries for signoff simulation. The VITAL Standard includes specialized routines for describing behavior and timing of ASIC cells and integrates backannotation via Standard Delay Format (SDF). One of the key issues of the VITAL initiative was to accelerate simulat...

In this paper we address the problem of software generation from a Hardware Description Language (HDL). In particular, we examine the issues involved in translating VHDL into C or C++ for use in system simulation and cosynthesis. Because of the concurrency supported by VHDL, and a notion of timing behavior, care must be taken to ensure behavioral correctness of the generated software. The issue...