This paper introduces a novel half-select resilient dual write wordline 8T (DW8T) SRAM with a sequential writing technique. The dual write wordlines are sequentially activated in a write cycle, and its combination with the half-VDD precharge suppresses the half-select problem. We implemented a 256-Kb DW8T SRAM and a half-VDD generator with a 40-nm CMOS process. The measurement results of the se...

The comparison and analysis of SRAM cells provides vital information for trading of design parameters to meet stringent requirements in the deep sub micron ranges. Initially this paper introduces to SRAM cells, then cell parametric dependences are investigated and finally simulation results of the same are shown. An 11T SRAM cell is compared with the conventional 6T SRAM cell for SNM, Power, DR...

This brief describes a new method to implement the singleport SRAM-based transpose memory for large size discrete cosine transform (DCT)/indiscrete cosine transform (IDCT) which are used in the latest video coding standard, such as high efficiency video coding. Instead of shift-register array or multiport SRAM, only single-port SRAM is used in the proposed design. A new diagonal data mapping sc...

In this paper a detailed study of the effect of the phase of noise has been done on 6T SRAM cell. The 6T SRAM has been subjected to different combinations of noises at the storage nodes and the read ability and write ability of the SRAM cell is examined considering different noise voltage levels. It is found that the effect is different under different combinations of the phases of the noise vo...

The explosive growth of battery operated devices has made lowpower design a priority in recent years Moreover, embedded SRAM units have become an important block in modern SoCs. Present day SRAMs are striving to increase bit counts while maintaining low power consumption and high performance. To achieve these objectives there is a need of continuous scaling of CMOS transistors, and so the proce...

A novel nine transistor (9T) CMOS SRAM cell design at 32nm feature size is presented to improve the stability, power dissipation, and delay of the conventional SRAM cell along with detailed comparisons with other designs. An optimal transistor sizing is established for the proposed 9T SRAM cell by considering stability, energy consumption, and write-ability. As a complementary hardware solution...

Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. Leakage is a serious problem particularly for SRAM which occupies large transistor count in most state-of-the-art chip designs. We propose a novel ultralow leakage SRAM design whi...

Static RAM cells are widely used for industrial and scientific subsystems, automotive electronics, etc .The power consumption of SRAM values depend on how frequently it is accessed. It can be power-hungry as dynamic RAM, when used at high frequencies. Integrated circuits consume higher watts at full bandwidth. In non-volatile SRAM and asynchronous SRAM, Power consumption limits its application....

In this paper we propose analytical models for estimating the leakage power in CMOS based SRAM designs. We identify the transistors that contribute to the leakage power in each SRAM sub-circuit as a function of the operation (read/write/idle) on the SRAM and develop parameterized leakage power models in terms of the high level design parameters and transistor widths. The models take number of r...

In this report, we aim to realize an ultra-low-power Static Random Access Memory (SRAM) realized on a different logic conversion block from traditional 6T SRAM, referring to Source-Coupled-Logic (SCL) based topology. It enables low supply voltage operation possible to effectively reduce power consumption according to the relationship, . The supply voltage in this report is lowered to 0.5V and t...