In this paper, I present FPGA implementation of a digital down converter (DDC) and digital up converter (DUC) for a single carrier WCDMA system. The DDC and DUC is complex in nature. The implementation of DDC is simple because it does not require mixers or filters. Xilinx System Generator and Xilinx ISE are used to develop the hardware circuit for the FPGA. Both the circuits are verified on the...

The concept of Image Processing is totally related to real time work, which is done by FPGA. Mathematical morphology is a well known image and signal processing technique. However, most morphological tools such MATLAB are not suited for strong real-time constraints. Application of FPGA Coprocessors as a means of delivering hardware IP to software and system engineers is presented. The hardware ...

This paper presents an area-efficient FPGA architecture for handshake-component-based design. The handshake-component-based design is suitable for largescale, complex asynchronous circuit because of its understandability. However, conventional FPGA architecture for handshake-component-based design is not area-efficient because of its complex logic blocks. This paper proposes an area-efficient F...

Design practices have an enormous impact on an FPGA design’s timing performance, logic utilization, and system reliability. Good design practices also aid in successful design migration between FPGA and ASIC implementations for both prototyping and production. Poor design practices can lead to low performance, high logic or resource utilization, and unstable or unreliable designs associated wit...

This paper presents a novel architecture of an asynchronous FPGA for handshake-component-based design. The handshake-component-based design is suitable for large-scale, complex asynchronous circuit because of its understandability. This paper proposes an area-efficient architecture of an FPGA that is suitable for handshakecomponent-based asynchronous circuit. Moreover, the FourPhase Dual-Rail e...

An AES algorithm is implemented on FPGA platform to improve the safety of data in transmission. AES algorithms can be implemented on FPGA in order to speed data processing and reduce time for key generating. We achieve higher performance by maintaining standard speed and reliability with low area and power. The 128 bit AES algorithm is implements on a FPGA using VHDL language with help of Xilin...

Conventional fault simulation techniques for FPGAs are very complicated and time consuming. The other alternative, FPGA fault emulation technique, is incomplete, and can be used only after the FPGA chip is manufactured. In this paper, we present efficient algorithms for computing the fault coverage of a given FPGA test configuration. The faults considered are opens and shorts in FPGA interconne...

The field programmable gate array (FPGA) technology provides programmable system-on-chip (PSoC) environments for designing modern digital ASIC controllers for specific applications. This paper presents a FPGA based speed control IC for three-phase induction motor drives. The sinusoidal PWM is realized on a single FPGA chip from Xilinx Inc. to provide controlling switching pulses for inverter bl...

It is well known that Field Programmable Gate Arrays (FPGAs) can be used to accelerate calculations that take too much time on a Central Processing Unit (CPU). Methodologies have been proposed to reconfigure the FPGA at run time, depending on the needs of the system. The CPU and FPGA generally communicate through message passing, letting the programmer decide exactly which data needs to be pass...