Conventional full-custom reconfigurable logic device design and implementation are time consuming processes. In this research, we propose a design framework in order to improve FPGA IP core design efficiency by link academic FPGA design flow and commercial VLSI CADs based on the synthesizable method. A novel FPGA routing tool is developed in this framework, namely the EasyRouter. By using simpl...

The Generic Library for Adaptive Computing Environments (GLACE) consists of a comprehensive set of module generators currently targeting Xilinx XC4000 and Virtex devices. In contrast to other research efforts in this area, it provides detailed meta-data about the generated circuits (behavior, area, timing, topology etc.) using the active FLAME interface. All of the modules adhere to a common la...

Edge detection is necessary tool for extraction of information for further image processing operation. Many computer vision application use edge detectors as primary operators before high level image processing. Several algorithms are available for edge detection which makes use of derivative approach. Roberts, Prewitt , sobel, canny are some of the examples of edge detection methods. In this p...

Ultra high-speed block turbo decoder architectures meet the demand for even higher data rates and open up new opportunities for the next generations of communication systems such as fiber optic transmissions. This paper presents the implementation, onto an FPGA device of an ultra high throughput block turbo code decoder. An innovative architecture of a block turbo decoder which enables the memo...

Актуальність. Аналіз даних, зокрема їх класифікація) часто виконується за допомогою методів машинного навчання. Часто задіяні алгоритми потрібні мати справу з великими наборами що призводить до тривалого часу виконання. Таким чином, актуальним є дослідження апаратних прискорювачів, на базі програмованої вентильної матриці (FPGA) для покращення продуктивності. FPGA перспективним рішенням апаратн...

In this paper we present a solution where only one FPGA is needed in a host coupled system, in which the FPGA can be reconfigured by a user application during run-time without loosing the host link connection. A hardware infrastructure on the FPGA and the software framework ACCFS (ACCelerator File System) on the host system is provided to the user which allow easy handling of reconfiguration an...

This paper proposes a kind of project which is about FPGA (the Field Programmable Gate Array, FPGA) hardware implementation scheme for PID AQM algorithm. According to the analyses of the relatively mature discrete PID algorithm, we realized PID algorithm by using the combination of LPM (Library of Parameter Modules) macro module and Verilog code in FPGA. In this article, we write the program of...