Design of a Low Power Magnetic Memory in the Presence of Process Variations

With the advancement in technology and shrinkage of transistor sizes, especially in technologies below 90 nm, one of the biggest problems of the conventional CMOS circuits is the high static power consumption due to increased leakage current. Spintronic devices, like magnetic tunnel junction (MTJ), thanks to their low power consumption, non-volatility, compatibility with CMOS transistors, and the possibility of high density construction, are one of the alternative candidates for designing hybrid MTJ / CMOS circuits. In recent years, several magnetic memories have been designed and implemented using MTJs, these memories suffer from problems like high power consumption and low speed. In this paper, a new writing circuit for reducing the power consumption of the circuit and some modifications in the write circuits to reduce static power are proposed. Simulation results suggest that the proposed memories offer up to 97% lower static power consumption and up to 71% lower dynamic power consumption than previous counterparts.