C. S. Vinitha
Electronics and Communication Engineering Department, Ambedkar Institute of Advanced Communication Technologies and Research (GGSIP University), Geeta Colony, Delhi, India.
[ 1 ] - An Efficient LUT Design on FPGA for Memory-Based Multiplication
An efficient Lookup Table (LUT) design for memory-based multiplier is proposed. This multiplier can be preferred in DSP computation where one of the inputs, which is filter coefficient to the multiplier, is fixed. In this design, all possible product terms of input multiplicand with the fixed coefficient are stored directly in memory. In contrast to an earlier proposition Odd Multiple Storage ...
Co-Authors