Reza Hosseini
Department of Electrical Engineering, Khoy Branch, Islamic Azad University, Khoy, Iran
[ 1 ] - Device and Circuit Performance Simulation of a New Nano- Scaled Side Contacted Field Effect Diode Structure
A new side-contacted field effect diode (S-FED) structure has beenintroduced as a modified S-FED, which is composed of a diode and planar double gateMOSFET. In this paper, drain current of modified and conventional S-FEDs wereinvestigated in on-state and off-state. For the conventional S-FED, the potential barrierheight between the source and the channel is observed to b...
[ 2 ] - Performance Study and Analysis of Heterojunction Gate All Around Nanowire Tunneling Field Effect Transistor
In this paper, we have presented a heterojunction gate all around nanowiretunneling field effect transistor (GAA NW TFET) and have explained its characteristicsin details. The proposed device has been structured using Germanium for source regionand Silicon for channel and drain regions. Kane's band-to-band tunneling model hasbeen used to account for the amount of band-to...
[ 3 ] - Design and Simulation of a 2GHz, 64×64 bit Arithmetic Logic Unit in 130nm CMOS Technology
The purpose of this paper is to design a 64×64 bit low power, low delay and high speed Arithmetic Logic Unit (ALU). Arithmetic Logic Unit performs arithmetic operation like addition, multiplication. Adders play important role in ALU. For designing adder, the combination of carry lookahead adder and carry select adder, also add-one circuit have been used to achieve high speed and low area. In mu...
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