Analysis and study of geometrical variability on the performance of junctionless tunneling field effect transistors: Advantage or deficiency?

This study investigates geometrical variability on the sensitivity of the junctionless tunneling field effect transistor (JLTFET) and Heterostructure JLTFET (HJLTFET) performance. We consider the transistor gate dielectric thickness as one of the main variation sources. The impacts of variations on the analog and digital performance of the devices are calculated by using computer aided design (CAD) tools. The gate oxide thickness is varied uniformly from right to left and vice versa and the performance of devices are analyzed. It is shown that changes in the geometric dimensions of the devices improves some electrical parameters and degrades others. Finally, we use the oxide thickness variation advantage and implement the oxide pocket close to the drain-channel interface for proposing of the pocket in narrower drain side oxide HJLTFET (PNS-HJLTFET).