طراحی PLL دو حلقه ای مبتنی بر آشکارسازی فاز پنجره‌ای با سرعت قفل بالا، توان مصرفی و اسپور مرجع پایین

In this paper, a dual loop PLL with short locking time, low power consumption and low reference spur is presented. The output frequency and reference frequency of the designed circuit are 3.2 GHz and 50 MHz, respectively, aimed to WiMAX applications. In the proposed circuit in locked state, some parts of the circuit could be powered off, to reduce overall power consumption. Phase detection in the circuit is based on Aperture Phase Detection (APD) method. In addition, the proposed charge pump reduces reference spur. The proposed structure of the frequency locked loop reduces the locking time. To evaluate the proposed approch, we simulated the designed PLL using the foundry design kit for 0.18μm CMOS technology.  The spur level and lock time of the proposed circuit is -74dBc and  1.9 μs, respectively, implying 5dB improvement in spur level and 32% improvement in lock time compared with the previously proposed circuits. The power consumption of the proposed circuit is 4.15 mW.