VLSI Design, Optimization, and Implementation of Channel Decoding in Wireless Systems

Today’s mobile information society has a steady demand for everincreasing data rates and better quality-of-service in wireless systems. To meet this demand standards organizations involved with the wireless industry are increasingly relying on modern high-performance channel codes such as low-density parity-check (LDPC) and turbo codes. These forward error-correction codes achieve near-optimal performance and thus enable highly robust wireless information transfer. Unfortunately, the excellent error-correction capabilities of LDPC codes and turbo codes come at the expense of substantial computational complexity in mobile receivers as the decoding of these codes is based on sophisticated iterative algorithms. In addition, practical decoder implementations must usually support a wide range of operation modes in order to enable the wireless system to adapt to various transmission environments. This combination of high computational requirements and high flexibility demands renders the implementation of LDPC and turbo decoders for wireless systems a considerable research challenge. During the last decade, significant progress has been made in the development of low-complexity LDPC and turbo decoding algorithms and the implementation of these algorithms in flexible dedicated very-large-scale integration (VLSI) circuits. Nevertheless, the implementation complexity of LDPC and turbo decoders remains high. Typically, these decoders are found among the most area and power intensive components in wireless baseband receivers and thus significantly strain the tight cost and power budgets of mobile batterypowered devices. Hence, the main part of this thesis is concerned with reducing the high VLSI implementation costs associated with LDPC and turbo