Architectures rapides dynamiquement reconfigurables des filtres numériques récursifs 1-D et 2-D Fast dynamically reconfigurable architectures for 1-D and 2-D recursive digital filters

and key words In this paper, we consider the array processors implementation of the infinite impulse response (11R)1-D and 2-D digital filters that require recursive computations . We use the state space representation to obtain, in a straight forward manner, efficient implementation via dynamically switchable systolic arrays (cylindrical type) of 1 -D direct realisation . This direct description leads to reduce the computation speed and the throughput rate . In order to improve, in a general way, the throughput rate performance of recursive filtering arrays, the solution proposed, in this paper, is based on the CTP decomposition technique of Porter which transforms the matrix-column product on a triple matrix product . It is shown in this work that this technique allows a realisation of IIR filters via dynamically reconfigurable cylindrical architectures that are much faster. However, this throughput improvement is obtained in the cost of a hardware complexity . The use of a sparse matrix of the tridiagonal type with the CTP decomposition permits a significant improvement of the hardware complexity of recursive filter arrays . Recursive digital filters, array processors, systolic, cylindrical, state space, sparse matrix, throughput, latency . Architectures des filtres numériques récursifs