Efficient approaches to testing VHDL DSP models

Modelling and Mitigation of Soft-Errors in CMOS Processors

The topic of this thesis is about soft-errors in digital systems. Different aspects of soft-errors have been addressed here, including an accurate simulation model to emulate soft-errors in a gate-level net list, a simulation framework to study the impact of soft-errors in a VHDL design and an efficient architecture to minimize the impact of soft-errors in a DSP processor. The first two chapter...

Behavioral Modeling and Simulation of Semiconductor Devices and Circuits Using VHDL-AMS

During the past few years, a lot of work has been done on behavioral models and simulation tools. But a need for modeling strategy still remains. The VHDL-AMS language supports the description of analog electronic circuits using Ordinary Differential Algebraic Equations (ODAEs), in addition to its support for describing discrete-event systems. For VHDL-AMS to be useful to the analog design ...

A Test Planning System for Functional Validation of VHDL DSP Models

An Efficient CPU Architecture for DSP Processors

Design narrative of an efficient CPU architecture dedicated to UTS-DSP (University of Tehran and Iran Communication Industries(SAMA) DSP) [1]-[10] is reported. Time and area consuming, the CPU architecture is a critical component of the overall architecture, which is responsible for execution of arithmetic and logical operations. The goal is composing an optimized hardware appropriate for execu...

System Level Virtual Prototyping of DSP SOCs Using Grammar Based Approach

As we move from algorithm on a chip to system on a chip era, the design bottleneck is shifting from individual DSP functions to global control that composes a system from these functions. The practice in industry suffers from global control entering the design flow too late, discontinuity between functional modeling and implementation phase and mixing data flow with global control. MASIC—Maths ...