Implementing a Scalable ASC Processor

Previous papers [1,2] have described our implementation of a small prototype processor and control unit for associative computing, called the ASC Procesor. That initial prototype was implemented on an Altera education board using an Altera FLEX 10K FPGA, and was limited to an unrealistic 4 Processing Elements (PEs). This paper describes a more complete implementation — a scalable ASC processor that can scale up to 52 PEs on an Altera APEX 20KE board, or further on larger FPGAs. This paper also proposes extensions to support multiple control units and control parallelism.