0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS
نویسندگان
چکیده
Digital LDO is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The developed digital LDO in 65nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-μA quiescent current at 200-μA load current. Both the input voltage and the quiescent current are the lowest values in the published LDO’s, which indicates the good energy efficiency of the digital LDO at 0.5-V operation.
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