Power & Area Efficient Router in 2-D Mesh Network-on-Chip Using Low Power Methodology - Clock Gating Techniques

Network-on-Chip (NoC) is the interconnection platform that answers the requirements of the modern on-Chip design. Small optimizations in NoC router architecture can show a significant improvement in the overall performance of NoC based systems. Power consumption, area overhead and the entire NoC performance is influenced by the router buffers. Resource sharing for on-chip network is critical to reduce the chip area and power consumption.An area efficient implementation of a routing node for a NoC is presented. Of the four components of routing node, the input block (mainly consisting of buffers) and scheduler have been modified to save area requirements. The other two components of the routing node take up negligible area in comparison. The use of custom SRAM in place of synthesizable flip flops in the input block has resulted in a saving of over 26% of the silicon area and power optimization is 65% when operated at 16 ns clock. Clock gating is an important high-level technique for reducing the power consumption of a design. Clock gating reduces the clock network power dissipation, relaxes the datapath timing, and reduces routing congestion by eliminating feedback multiplexer loops. For designs that have large multi-bit registers, clock gating can save power and reduce the number of gates in the design. In our design case, it has been further observed that the power optimization with clock gating techniques at RTL level saves 67.38%, Gate Level 67.29% & Power Driven around 68.79% of power while 30.38 %, 27.85 % &31.21% silicon area respectively have been saved.