Low Power Content Addressable Memory with Pre- Comparison Sceheme and Dual-vdd Techmique

A low power content addressable memory is designed by the pre-comparison scheme, power gating and dual-VED techniques. With the pre-comparison scheme, it will reduce the discharging time and power consumption when the match line is mismatch. Furthermore, the techniques of power gating and dual VDD are applied to the pre-comparison CAM to reduce the leakage power. The size of the CAM array is about 32 words, and each word has 32bits. The proposed pre-comparison NORtype 10T CAM can achieve 22.8% dynamic power reduction for the 4bits pre-comparison circuit and 33.4% leakage power reduction with power gating and dual VDD techniques. All the simulation results are based on TSMC 100 nm CMOS technology and the clock frequency is 500MHz.