An Efficient VLSI Architecture for MC Interpolation in AVC Video Coding

Advance Video Coding (AVC) has employed a 6-tap interpolation FIR filter in its motion compensation (MC) part for high coding efficiency. But it is accompanied by increasing the complexity in calculation and the number of memory access. And this problem makes MC one of the bottlenecks in the AVC system’s VLSI implementation, especially for SDTV/HDTV which aggravate the problem heavily. Unfortunately, most FIR filter [8][9][10] have too low of input bandwidth to deal with it. In this paper, an efficient architecture for MC interpolation is described, and experimental results show that this architecture satisfies AVC decoder applications such as SDTV or HDTV.