Efficient polygon enclosure algorithms for device extraction from VLSI layouts

The typical description of a VLSI layout is the geometrical description of masks. Layout verification [4] is the testing of a layout to see if it satisfies design and layout rules. An important problem in layout verification is layout device extraction, which involves detection of capacitors, resistors, transistors etc. from the geometrical description of masks. The layout extraction process starts with a circuit layout and based on user-defined relationship information and it proceeds to detect electrical components from the geometrical relationships of the layout. In this paper we consider the extraction of BJT (bipolar junction transistor) devices.