Design of Digital Filter using Low Power and Area Efficient SQRT CSLA

The demand of delivering faster, portable and highly reliable products is the major goal of low power VLSI subsystems and it cannot be maintained in all the situations. But it can be optimized to a certain extent by controlling some of the factors. Design of area and power efficient high speed data path logic systems are one of the substantial researches and the most crucial parameter that requires ultimate attention is power consumption. With high power dissipation the reliability of the product is very much degraded. The second concern depends on area. Area should also be taken into concern for low power applications. Adders are designed in such a way which can effectively reduce the propagation delays, which is the major cause of power consumption. Carry Select Adder (CSLA) is one of the fastest adders used in many data processing processors to perform fast arithmetic functions. The structure of conventional CSLA is modified to achieve low power and area. This work proposes the development of improved SQRT CSLA from conventional SQRT CSLA and realization of digital filter using this improved SQRT CSLA. This improved SQRT CSLA is simulated for 16,32,48,64 and 128–b using Xilinx/Mentor Graphics tool. Its performance is measured and compared with conventional SQRT CSLA in terms of area and power.