Logic Diagnosis-Diversion or Necessity?

Failure diagnosis is resource intensive, frustrating, and often impossible. However, it is also critical and necessary for aggressive designs and manufacturing processes. Research in this area is making rapid progress, but the challenges are also rapidly growing in magnitude and importance. 1 The Problem and Necessity Failure diagnosis incorporates all of the interesting problems present in classical pass/fail testing with at least an order of magnitude increase in difficulty. Test generation, fault simulation, and design for test are not only significantly more challenging when failure analysis is the objective, but they are also only part of the problem. Failure analysis relies on precision accuracy, intensive data collection, and extensive knowledge of the design and manufacturing process. Memory diagnosis is a solved problem and profitable venture due to the complete observability and controllability of each memory cell and the simple repetitive design structure. A direct correlation between output responses and process improvement can be made with little physical inspection. Failure diagnosis for integrated circuits composed primarily of sequential logic is an unsolved problem and often unprofitable venture. CAD tools are fortunate when they can generate tests that detect faults and they are unlikely to provide tests that can accurately locate failures. There is little assistance in correlating error responses with improvements in manufacturing. The challenge is tempered by the necessity. Aggressive integrated circuit architectures must be coupled with initially unstable manufacturing processes in the context of time-to-market demands. Profit margins are also correlated tightly with manufacturing yield. The choice is not whether fault diagnosis will be performed, but whether the diagnosis will be rapid, accurate, cost effective, and to what degree it will be automated. This research was supported in part by Defense Advanced Research Projects Agency (DARPA) under contract DABT 63-96-C-0069, by the Semiconductor Research Corporation (SRC) under grant 94-DP109, by the Office of Naval Research (ONR) under grant N0001495-1-1049, and by an equipment grant from Hewlett-Packard. 2 Progress and Failures Promising results have been reported at ITC, ICCAD, VTS, and FTCS by several research and industrial groups on significant components of the fault diagnosis problem. The state of the art in CAD tools for diagnostic test generation, fault simulation, and design for diagnosis is similar to the state of the art in ATPG approximately five years ago. Dramatic improvements have been reported in generating accurate tests, evaluating the efficiency of diagnostic tests, speeding up the time it takes to perform a diagnosis, and in creating and processing compact fault dictionaries. Limited progress is being made in developing CAD tools for failures that cannot be modeled by stuck-at faults. No solution is in sight for automatic diagnosis of sequential circuits composed of millions of transistors. 3 Opportunities The major impediment to fault diagnosis has been a lack of progress in research on classical ATPG (test generation, fault simulation, and design for test). When available, results from ATPG have been rapidly incorporated into fault diagnosis tools in the last five years. There have been several recent examples where research on failure diagnosis has actually provided important new results in classical fault detection. Tests designed for failure analysis have been shown to provide higher fault coverage than standard fault detection tests. Failure analysis must also by necessity form links with problems and results in other areas of design and manufacturing. For example, the art of design debugging and the science of verification are intertwined with failure analysis in the early stages of an aggressive manufacturing process. Errors encountered during manufacturing tests may be due to faulty logic design, architecture specification errors, manufacturing process problems, or spot defects. Ideally, the fault diagnosis process will integrate physical failure location with design debugging. Finally, the design flow must be modified to include failure diagnosis. Diagnostic accuracy and speed can often be enhanced at no additional performance or area cost by modifying and exploiting the design for test structures already incorporated in the architecture. Proceedings of the Proceedings International Test Conference 1997 (ITC’97) 1089-3539/97 $10.00 © 1997 IEEE