Network Parameters Performance Evaluation & Simulation for Noc Architecture
نویسنده
چکیده
Network on Chip (NoC) architecture attempts to address different component level architectures with specific interconnection network topologies and routing techniques, some of the topologies are CLICHE, Folded Torus, BFT. Only one distance vector routing used for different topologies. The work has not done with one routing for (CLICHE, Folded Torus and BFT) topologies. In this project we proposed link state routing and compares (CLICHE, Folded Torus, BFT) NoC architectures to evaluate their performance using a simulating tool NS-2. Simulation provides relationship among latency, throughput and packet drop probability for NoC architectures. Best one topology can be identifying by comparing various parameters. Keywords-Network on Chip, Different Topologies and topology parameter.
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