Design & Comparative Analysis of Dynamic Decoder and Tree Decoder

The key objective of this project is to design a decoder which can be used for hardware purpose. A decoder is a combinational circuit that converts binary information from n input lines to a maximum of m=2 output lines. In this paper are design of Dynamic decoder and Tree Decoder. Also shows a comparative analysis of tree decoder with corresponding dynamic decoder and tree decoder highlights the benefits of preferring tree decoders in digital system designs. Large tree decoder can be constructed by reusing smaller similar sub-modules. Thus the structure is symmetric. The symmetric and regular structure of tree decoder makes the system easy to design. The structure obeys regularity and modularity concepts of VLSI circuit. Digital communication systems have proven their efficiency and brought a new element in the chain of signal transmitting and receiving, the digital processor. The design to be implementing by using Verilog-HDL language. The Simulation and Synthesis by using ISE Xilinx 13.4 tool. Keywords-Tree Decoder, Dynamic Decoder, Verilog INTRODUCTION In any communication network, it is common we have two parts in which one is transmitter and other is receiver. At the receivers we use the decoders which are helpful in obtaining the desired information effectively. A decoder takes the coded information from a receive message and changes it into a recognizable form. A decoder is a combinational circuit that converts binary information from n input lines to a maximum of m=2n output lines. Design of a high performance and efficient static, dynamic and tree decoder is very important for design of a frequency allocator but the main point is to allocate the specified band to assign a set of inputs which is then obtained at the desired output, thus the developing of a reliable and fast frequency allocator is a big problem in itself. Static Decoder Static decoders are simple line decoders which can be implemented using basic logic gates. In a hardware based static decoder, the frequency allocation is done in such a manner that it allocates the spectrum to the service providers statically. By the service providers the services are further distributed to the different users respectively. Fig 1.1: 2 to 4 decoder INPUT OUTPUT A1 A0 B3 B2 B1 B0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0 Tab 1.1: Truth Table for 2 to 4 Decoder