Trends in R&D in TSV Technology for 3D LSI Packaging

Small, high-speed, and multi-functional computers and other electronic devices have been enabled by high integration technologies that have come to reality by the miniaturization through the LSI process scaling which uses a very fine pattern. However, an upper limit in the progress of such miniaturization has come into sight. The miniaturization will be technologically limited due to the increase of leak current which generates heat in transistors, and signal delay time caused by wiring. 3D packaging technology is one of the technologies that are expected to make a breakthrough such miniaturization on a 2D surface, which will enable high density integration that does not depend on miniaturization on 2D surfaces. By stacking LSI chips, which would conventionally be set out on a plane, it will be possible to produce LSI components, with the same functionality as that of the components produced by conventional methods, and with a smaller footprint. The 3D packaging key technologies are electrical packaging technology, which means that it is vital to connect the stacked chips electrically. Conventional 2