Integrated Test Scheduling, Test Parallelization and TAMDesign
نویسندگان
چکیده
We propose a technique integrating test scheduling, scan chain partitioning and test access mechanism (TAM) design minimizing the test time and the TAM routing cost while considering test conflicts and power constraints. Main features of our technique are (1) the flexibility in modelling the systems test behaviour and (2) the support for interconnection test of unwrapped cores and user-defined logic. Experiments using our implementation on several benchmarks and industrial designs demonstrate that it produces high quality solution at low computational cost.
منابع مشابه
System-on-Chip Test Parallelization Under Power Constraints
1 This paper deals with test parallelization (scan-chain subdivision) which is used as a technique to reduce test application time for systems-on-chip. An approach for test parallelization taking into account test conflicts and test power limitations is described. The main features of the proposed approach are the combination of test parallelization with test scheduling as well as the developme...
متن کاملOn Generating High Quality Tests for Transition Faults
ATS 2002 Integrated Test Scheduling, Test Parallelization and TAM Design Erik Larsson, Klas Arvidsson, Hideo Fujiwara and Zebo Peng On Generating High Quality Tests for Transition Faults Yun Shao, Irith Pomeranz and Sudhakar M. Reddy A Scheduling Method in High-Level Synthesis for Acyclic Partial Scan Design Tomoo Inoue, Tomokazu Miura, Akio Tamura, and Hideo Fujiwara Test Scheduling and Test A...
متن کاملAn Integrated System-Level Design for Testability Methodology
HARDWARE TESTING is commonly used to check whether faults exist in a digital system. Much research has been devoted to the development of advanced hardware testing techniques and methods to support design for testability (DFT). However, most existing DFT methods deal only with testability issues at low abstraction levels, while new modelling and design techniques have been developed for design ...
متن کاملUsing Knowledge-Based Techniques on Loop Parallelization for Parallelizing Compilers
In this paper we propose a knowledge-based approach for solving data dependence testing and loop scheduling problems. A rule-based system, called the K-Test, is developed by repertory grid and attribute ording table to construct the knowledge base. The K-Test chooses an appropriate testing algorithm according to some features of the input program by using knowledge-based techniques, and then ap...
متن کاملCASCH : A Tool for Computer - Aided
of parallelization—potentially improving their performance—and, because manually performing these tasks can be tedious, they also help experienced programmers. Even though a large body of literature exists in the area of scheduling and mapping 1–3 (see the “Recent research” sidebar), people have exploited only a part of it for practical purposes. While some have proposed software tools that sup...
متن کامل