ECE-599:Low Power, Adaptive Bandwidth Tracking Phase Locked Loop Design
نویسندگان
چکیده
A low power, adaptive bandwidth tracking Phase Locked Loop (PLL) is presented in this paper. Designed PLL operates over a wide frequency range of 250MHz to 1GHz with a fixed multiplication factor of 8. PLL is optimized for 0.2% UI of r.m.s. jitter over the whole frequency range with bandwidth tracking to keep the power consumption minimum. In addition, a multiplier block is used to increase the input frequency by two, which further increases the power efficiency of the PLL. The circuit is designed and simulated using 0.18μm process with supply voltage of 1.8V.
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