Layout Verification by Extraction for Micro Total Analysis Systems

The increasing complexity of Micro Total Analysis Systems (μTAS) is leading to a growing need for layout verification. Currently, verification involves numerical simulation, which is slow, memory consuming and impractical for large designs. An alternative is to couple layout extraction with emerging schematic-based simulation for verification of complex designs. This paper reports on a prototype μTAS layout extractor which automatically constructs a schematic from a given layout. The extractor presented is capable of handling non-Manhattan and curved geometry and includes recognition heuristics specific to μTAS designs. The utility of the extractor is demonstrated using selected designs.