A Design of Operational Amplifiers for Sigma Delta Modulators using O.35um CMOS Process

An operational amplifier designcd with O.35um CMOS teehnology is prcsented. All the transistors are realized with minimum or near-minimum ehannel length. As thc short ehannel length causcs performance degradation, a proper operational amplifier structure is sclected to compensate the performance degradation. The op amp is designed to meet the requirement of high-speed high-resolution sigma delta modulators. It has a folded-cascode first stage and a class-A output stage. lt features a DC gain of 78dB, an openloop unity-gain frequency of 266MHZ, a slew rate of 650V/us, and consumes IO.2mW from a +/-1.5V power supply. High level simulation is uscd to evaluatc the OT A performance in sigma delta modulators.