A Low complexity solution to the implementation of linear periodically time varying filters-FPGA implementation

This paper presents an area efficient architecture for a linear periodically time varying (LPTV) filter. It is developed from the output switching representation of LPTV filter. In this representation, an N-tap,M Period LPTV filter can be realized by M linear time invariant (LTI) filters of N taps each connected in parallel with an M periodic switch at the output. We devloped an area efficient architecture for LPTV filter from a single N tap LTI filter. We achieve this by distributing the coefficient memory. The proposed architecture utilizes N coefficient multipliers, whereas the conventional output switching realization needs NM multipliers. The proposed architecture is simulated, synthesized and implemented on Virtex FPGA.